Reconfigurable Hardware Synthesis of the IDEA Cryptographic Algorithm

The paper focuses on the synthesis of a highly parallel reconfigurable hardware implementation for the International Data Encryption Algorithm (IDEA). Currently, IDEA is well known to be a strong encryption algorithm. The use of such an algorithm within critical applications, such as military, requires efficient, highly reliable and correct hardware implementation. We will stress the affordability of such requirements by adopting a methodology that develops reconfigurable hardware circuits by following a transformational programming paradigm. The development starts from a formal functional specification stage. Then, by using function decomposition and provably correct data refinement techniques, powerful high-order functions are refined into parallel implementations described in Hoare’s communicating sequential processes notation(CSP). The CSP descriptions are very closely associated with Handle-C hardware description language (HDL) program fragments. This description language is employed to target reconfigurable hardware as the final stage in the development. The targeted system in this case is the RC-1000 reconfigurable computer. In this paper different designs for the IDEA corresponding to different levels of parallelism are presented. Moreover, implementation, realization, and performance analysis and evaluation are included.